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Author Rispoli, K. ♦ Gould, L. ♦ Mandry, J. ♦ Delivorias, P.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2006
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Process design ♦ Assembly ♦ Substrates ♦ Chip scale packaging ♦ Lead compounds ♦ Integrated circuit reliability ♦ Semiconductor device reliability ♦ CMOS integrated circuits ♦ Integrated circuit layout ♦ Electronic design automation and methodology
Abstract Instituting dimensional reductions in the layout of CMOS semiconductor chips can lead to unwanted conduction paths significant enough to impact the performance and reliability of the subsequent fabricated integrated circuit. Positive location and identification of the suspect areas is required for the determination of root cause and to enable corrective action to eliminate or minimize the unwanted conduction paths. Empirical methods have to be employed to identify suspect areas since EDA vendors do not have CAD tools sufficiently capable of identifying the suspect areas during the design phase of a complicated high performance integrated circuit. Applying varied thermal imaging procedures and analytical techniques on specially assembled bare chips with defined limited performance identified problematic chip substrate regions and subsequent current conduction through the substrate as the problem in those regions. Corrective chip design layout and assembly techniques were instituted to achieve the required isolation. Although corrective action was achieved through chip design layout modifications, an outline of the wafer processing technology employed will be presented to designate the questionable areas with possible fabrication alterations to avoid the conduction paths encountered
Description Author affiliation: Raytheon Co., Sudbury, MA (Rispoli, K.)
ISBN 1424401534
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2006-03-14
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 1.90 MB
Page Count 6
Starting Page 120
Ending Page 125


Source: IEEE Xplore Digital Library