Access Restriction

Author Storey, T.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1993
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Testing ♦ Very large scale integration ♦ Silicon ♦ Packaging ♦ Space technology ♦ Costs ♦ Substrates ♦ CMOS technology ♦ Power capacitors ♦ CMOS process
Abstract This paper describes a methodology developed to test high performance VLSI CMOS ICs that have been mounted onto a multichip silicon substrate. After a brief description of the package technology itself, the necessary elements of an ideal test methodology are provided, along with a description of the drawbacks of existing methods. The test strategy developed, covering test from the wafer level, unpopulated substrate, and populated substrate, is then detailed.
Description Author affiliation: IBM Corp., Manassas, VA, USA (Storey, T.)
ISBN 0780314301
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1993-10-17
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 1.02 MB
Page Count 10
Starting Page 359
Ending Page 368

Source: IEEE Xplore Digital Library