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Author Takemoto, T. ♦ Yuki, F. ♦ Yamashita, H. ♦ Tsuji, S. ♦ Saito, T. ♦ Nishimura, S.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2010
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword CMOS integrated circuits ♦ Bandwidth ♦ Driver circuits ♦ Gain ♦ Bit error rate ♦ Optical receivers ♦ Propagation losses
Abstract A 25 Gb/s × 4-channel transimpedance amplifier has been realized in 65-nm CMOS technology. It achieves transimpedance gain of 69.8 dBΩ, bandwidth of 22.8 GHz, and gains flatness of under ±2 dB after equalizing the effect of transmission loss, incorporating gain-stage amplifier with flat frequency response, and 50Ω-output driver with an analogue equalizer. The proposed TIA dissipates only 74 mW/ch and demonstrates the transimpedance bandwidth products per DC power of 952.1 GHzΩ/mW and crosstalk of less than −17 dB. The sensitivity at bit error rate (BER) of less than $10^{−12}$ was measured to be the optical input power of −7.4 dBm for multi-channel operation at the data rate of 25 Gb/s, and also demonstrates only 0.8 dB power penalty.
Description Author affiliation: Central Research Laboratory, Hitachi, Ltd., 1-280 Higashi-koigakubo Kokubunji-shi, Tokyo, 185-8601, Japan (Takemoto, T.; Yuki, F.; Yamashita, H.; Tsuji, S.; Saito, T.; Nishimura, S.)
ISBN 9781424457588
ISSN 21523630
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2010-09-19
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
e-ISBN 9781424457601
Size (in Bytes) 237.37 kB
Page Count 4
Starting Page 1
Ending Page 4


Source: IEEE Xplore Digital Library