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Author Islam, M.R. ♦ Babu, H.M.H. ♦ Mustafa, M.A.R. ♦ Shahriar, M.S.
Sponsorship IEEE Comput. Sci. Test Technol. Tech. Council
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2003
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Programmable logic arrays ♦ Logic design ♦ Logic circuit testing ♦ Design for testability
Abstract In this paper, an improved design of easily testable PLAs has been proposed, based on input decoder augmentation using pass transistor (PT) logic along with improved conditions for product line grouping. The proposed technique primarily increases the fault coverage area of easily testable PLAs due to augmented PT and reduced testing time due to grouping the product lines. A simultaneous testing technique has been applied within the group that reduces the testing time. This approach ensures the detection of certain bridging faults, which were not considered by the existing techniques. A modified testing technique has also been presented in this paper. It is shown that the new grouping technique enhances the devices in all respects.
Description Author affiliation: Dept. of Comput. Sci., Dhaka Univ., Bangladesh (Islam, M.R.; Babu, H.M.H.; Mustafa, M.A.R.; Shahriar, M.S.)
ISBN 0769519512
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2003-11-16
Publisher Place China
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 216.97 kB
Page Count 4
Starting Page 90
Ending Page 93

Source: IEEE Xplore Digital Library