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Author Chiu, E.H. ♦ An, Q.D.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1991
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword BiCMOS integrated circuits ♦ Technical Activities Guide -TAG ♦ Random access memory ♦ Impedance matching ♦ Read-write memory ♦ Cache memory ♦ Energy consumption ♦ Microprocessors ♦ CMOS process ♦ CMOS technology
Abstract A highly-integrated 88-kb two-way set associative cache tag memory fabricated using 0.8- mu m BiCMOS technology has been developed. The device integrates two 8 K*5 RAMs for tag and parity storage, one 8 K*1 least recently used (LRU) RAM, and the associated cache interface control logic. The die area is 4.9 mm*6.9 mm. Address to MATCH delay is 10 ns, and all three RAM cells can be reset in less than 8 ns. In addition, active power consumption is less than 750 mW at 5 V.<<ETX>>
Description Author affiliation: Texas Instrum. Inc., Dallas, TX, USA (Chiu, E.H.; An, Q.D.)
ISBN 0780300157
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1991-05-12
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 246.36 kB


Source: IEEE Xplore Digital Library