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Author Shijian Zhang ♦ Weiwu Hu
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2007
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Registers ♦ Fault detection ♦ Retirement ♦ Hardware ♦ Costs ♦ Delay ♦ Pipelines ♦ Buffer storage ♦ Redundancy ♦ Yarn
Abstract Conventional temporal redundant techniques to detect transient faults have resulted in considerable performance loss. One major reason for this problem is the reclamation of some critical resources, such as the instruction window and physical registers, is delayed, which degrades instruction-level parallelism. This paper proposes a novel fault-tolerant micro-architecture based on checkpoint mechanism. All occupied resources are reclaimed during the retirement stage in the first execution. Therefore, the performance overhead is mitigated evidently. Our scheme requires only small hardware cost and provides short fault detection latency.
Description Author affiliation: Chinese Acad. of Sci., Beijing (Shijian Zhang; Weiwu Hu)
ISBN 9780769528908
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2007-10-08
Publisher Place China
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 316.29 kB
Page Count 6
Starting Page 313
Ending Page 318

Source: IEEE Xplore Digital Library