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Author Vashchenko, V.A. ♦ Lindorfer, P. ♦ Hopper, P.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2005
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics
Subject Keyword Electrostatic discharge ♦ MOS devices ♦ Low voltage ♦ Thyristors ♦ Clamps ♦ Conductivity ♦ Protection ♦ Threshold voltage ♦ Implants ♦ Circuits
Abstract A novel design approach for low-voltage ESD protection clamps is suggested based on the use of free pseudo high threshold voltage SCR structures. The method is experimentally validated for a 0.18 mum 1.8 V/5 V dual gate oxide CMOS process where free high threshold voltage $(V_{T})$ LVTSCR and Drain extended NMOS-SCR structures were formed by combining the thick 120 A gate oxide used for 5 V devices with additional low voltage PWELL through poly implants used for the 1.8 V devices. The physical mechanism of the forming of pseudo high $V_{T}$ characteristics is explained by means of numerical simulation. Low-voltage pulsed turn-on and turn-off characteristics have been demonstrated under low DC leakage of the devices.
Description Author affiliation: Nat. Semicond. Corp., Santa Clara, CA, USA (Vashchenko, V.A.; Lindorfer, P.; Hopper, P.)
ISBN 9781585370696
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2005-09-08
Publisher Place USA
Rights Holder EOS/ESD Association, Inc.
Size (in Bytes) 328.04 kB
Page Count 6
Starting Page 1
Ending Page 6

Source: IEEE Xplore Digital Library