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Author Buchenrieder, K. ♦ Pyttel, A. ♦ Sedlmeier, A.
Sponsorship EDAA
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2002
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Design engineering ♦ Power engineering and energy ♦ Hardware ♦ Object oriented modeling ♦ Field programmable gate arrays ♦ Algorithm design and analysis ♦ Prototypes ♦ Design methodology ♦ Design automation ♦ Decoding
Abstract In this papers we present an efficient methodology to validate high performance algorithms and prototype them using reconfigurable hardware. We follow a strict top-down Hardware/Software Codesign paradigm using stepwise refinement techniques. Starting from a performance, evaluation on the data-flow level using the OCAPI system, we partition the simulated high-level data-flow description into hardware and software modules. The hardware parts, described in Handel-C, are compiled and mapped to Xilinx Virtex 2000E FPGAs, and the software is executed on a PC processor that hosts the Virtex boards. Hardware/Software interfacing, and communication between processor and FPGA is established via the PCI bus by shared memory DMA transfers. This paper presents the methodology and illustrates the method with an example of a channel coder.
Description Author affiliation: Corporate Dev., Infineon Technol. AG, Munich, Germany (Buchenrieder, K.)
ISBN 0769514715
ISSN 15301591
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2002-03-04
Publisher Place France
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 228.79 kB
Page Count 5
Starting Page 870
Ending Page 874

Source: IEEE Xplore Digital Library