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Author Whetsel, L.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1994
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Life estimation ♦ Circuit testing ♦ Integrated circuit testing ♦ Logic testing ♦ Combinational circuits ♦ System testing ♦ Clocks ♦ Shift registers ♦ Instruments ♦ Sequential analysis
Abstract This paper describes an approach which can accelerate scan testing of combinational and sequential circuits within IEEE 1149.1 architectures. The approach can be used at both IC and system test levels, however most of the test time reduction benefits of this approach are seen at the system level.
Description Author affiliation: Texas Instrum. Inc., USA (Whetsel, L.)
ISBN 0780321030
ISSN 10893539
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1995-10-02
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 901.62 kB
Page Count 9
Starting Page 314
Ending Page 322


Source: IEEE Xplore Digital Library