Access Restriction

Author Anderson, T.L.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1997
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Chip scale packaging ♦ Sockets ♦ Standards organizations ♦ Protocols ♦ Logic design ♦ Microprocessors ♦ Application specific integrated circuits ♦ Semiconductor devices ♦ Semiconductor device testing ♦ Production
Abstract A number of initiatives have begun to address the integration and test of core-based chip design. Several organizations, including an IEEE Test Technology Technical Committee (TTTC) and working groups of the Virtual Socket Interface Alliance (VSIA), meet regularly to consider standards and solutions. The most immediate issue that a chip designer must face is the integration of a core (or cores) into the chip. Three main approaches are popular. FIFO-based interfaces are quite common for VO interconnect cores; they have simple protocol rules and mate up well with DMA designs in the application logic. The core might instead mate to a microprocessor or I/O bus. For example, a multi-function chip can use an on-chip PCI bus to connect together multiple cores with PCI interfaces. The final common approach is a bus defined explicitly by an ASIC vendor or core provider to interconnect cores. For all three types of core interconnection, handling functional operation is only half of the solution. As with all semiconductor devices, a core-based chip must be well tested in production to become a viable product.
Description Author affiliation: Phoenix Tech. Ltd., AZ, USA (Anderson, T.L.)
ISBN 0780342097
ISSN 10893539
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1997-11-06
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 106.54 kB

Source: IEEE Xplore Digital Library