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Author Bosio, A. ♦ Di Natale, G.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2008
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Open source software ♦ Circuit faults ♦ Circuit simulation ♦ Discrete event simulation ♦ Logic testing ♦ Circuit testing ♦ Single event upset ♦ Logic circuits ♦ Performance evaluation ♦ Digital circuits ♦ Open-source ♦ Fault simulator ♦ logic simulation
Abstract This paper presents LIFTING (LIRMM fault simulator), an open-source simulator able to perform both logic and fault simulations for single/multiple stuck-at faults and single event upset (SEU) on digital circuits described in Verilog. Compared to existing tools, LIFTING provides several features for the analysis of the fault simulation results, meaningful for research purposes. Moreover, as an open-source tool, it can be customized to meet any user requirements. Experimental results show how LIFTING has been exploited on research fields. Eventually, execution time for large circuit simulations is comparable to the one of commercial tools.
Description Author affiliation: Lab. d'lnf., Univ. Montpellier II, Montpellier (Bosio, A.; Di Natale, G.)
ISBN 9780769533964
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2008-11-24
Publisher Place Japan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 398.58 kB
Page Count 6
Starting Page 35
Ending Page 40


Source: IEEE Xplore Digital Library