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Author Badura, D. ♦ Hlawiczka, A.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1997
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Costs ♦ Built-in self-test ♦ Circuit testing ♦ Circuit faults ♦ Registers ♦ Test pattern generators ♦ Sequential circuits ♦ Automatic testing ♦ Flip-flops ♦ Error correction
Abstract An application of new idea of designing circular self-test path (CSTP) for EDAC circuit is given in the paper. The new BIST scheme called in the paper as a condensed circular self-test path (CCSTP=C/sup 2/STP) makes possible to reduce significantly the number of CBIST cells to a smaller value. We focus on the analysis of the state transition graph (STG) as a key to understand the state coverage, fault coverage, and zero aliasing of condensed circular BIST (CBIST) schemes. There are given two examples of C/sup 2/BIST design. Particularly, the simple example of C/sup 2/STP design for 4-bit errors detection and errors correction (EDAC) circuit indicates advantages of such BIST technique. On the basis of this example it is shown that the time and complexity of simulation process for C/sup 2/STP is smaller than those for CSTP configuration and the seek time of a solution giving quasi optimal effectiveness for C/sup 2/STP is considerably shorter.
Description Author affiliation: Inst. of Appl. Comput. Sci., SU of Katowice, Poland (Badura, D.)
ISBN 0818682094
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1997-11-17
Publisher Place Japan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 384.88 kB
Page Count 6
Starting Page 410
Ending Page 415


Source: IEEE Xplore Digital Library