Access Restriction

Author Bennour, I.E. ♦ Aboulhamid, E.M.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1995
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science ♦ Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics
Subject Keyword Hardware ♦ Clocks ♦ Pipeline processing ♦ Throughput ♦ Equations ♦ Length measurement ♦ Flow graphs ♦ Polynomials ♦ Circuit synthesis ♦ Scheduling
Abstract The performance of pipelined designs is measured basically by three values: the clock cycle length, the initiation interval and the iteration time. In this paper we present a new technique for computing the maximal performance of pipelined implementation. Given a data flow graph specification and a set of resources, we derive lower bounds of the initiation interval and the iteration time achievable by any pipelined implementation.
Description Author affiliation: Dept. d'Inf. et de Recherche Oper., Montreal Univ., Que., Canada (Bennour, I.E.; Aboulhamid, E.M.)
ISBN 0780327667
ISSN 08407789
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1995-09-05
Publisher Place Canada
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 410.38 kB
Page Count 4
Starting Page 632
Ending Page 635

Source: IEEE Xplore Digital Library