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Author Storey, T.M. ♦ Maly, W.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1990
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Fault detection ♦ Testing ♦ Costs ♦ Test pattern generators ♦ Design automation ♦ Analog-digital conversion ♦ Analytical models ♦ Monitoring ♦ Semiconductor device modeling ♦ Current measurement
Abstract The authors compare the performance of two test generation techniques, stuck fault testing and current testing, when applied to CMOS bridging faults. Accurate simulation of such faults mandated the development of several new design automation tools, including an analog-digital fault simulator. The results of this simulation are analyzed. It is shown that stuck fault test generation, while inherently incapable of directly expressing many of the likely CMOS faults, was still able to generate a set of effective test patterns. Current monitoring, however, by virtue of its more accurate model and less stringent detection criterion, was able to generate tests of measurably higher quality. It is concluded that the selection of one technique over the other becomes a cost tradeoff. Current testing produced test patterns that were consistently more effective in detecting bridging faults. This higher quality comes at higher start-up costs aid higher costs per chip design.
Description Author affiliation: Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA, USA (Storey, T.M.; Maly, W.)
ISBN 081869064X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1990-09-10
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 950.36 kB
Page Count 10
Starting Page 842
Ending Page 851


Source: IEEE Xplore Digital Library