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Author Saeki, T. ♦ Minami, K. ♦ Yoshida, H. ♦ Suzuki, H.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1998
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Mirrors ♦ Application specific integrated circuits ♦ Clocks ♦ Delay lines ♦ Driver circuits ♦ Propagation delay ♦ Delay effects ♦ Timing ♦ Synchronization ♦ Phase locked loops
Abstract This paper describes a new concept nonfeedback CMOS digital clock generator, Direct SMD, that achieves clock deskew in only two clock cycles for ASICs having unfixed and various clock paths. The Direct SMD detects clock skew as well as clock cycle by introducing direct skew detector and clock suspension circuitry. The direct skew detection scheme completely removes the phase error caused by the delay fluctuation of the clock driver. The measured results demonstrate that the Direct SMD can successfully eliminate various amounts of clock skew (2.0 ns-3.0 ns) at 200 MHz in two clock cycles.
Description Author affiliation: ULSI Device Dev. Labs., NEC Corp., Kanagawa, Japan (Saeki, T.)
ISBN 0780342925
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1998-05-14
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 506.97 kB
Page Count 4
Starting Page 511
Ending Page 514

Source: IEEE Xplore Digital Library