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Author Chia-Cheng Lo ♦ Ying-Jhong Zeng ♦ Ming-Der Shieh
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2007
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Testing ♦ Encoding ♦ Hardware ♦ Arithmetic ♦ Clocks ♦ Throughput ♦ Video sequences ♦ Manufacturing ♦ Context modeling ♦ Bit rate
Abstract The inherent data dependency and various types of syntax elements existing in the CABAC encoding process will result in dramatically increased complexity if two bins obtained from binarizing syntax elements are handled per clock cycle. By analyzing the distribution of binarized bins in different video sequences, we show how to efficiently improve the encoding rate with a limited increase in hardware complexity by only allowing a certain type of syntax elements to be processed two bins at a time. Together with the presented range renovation reordering and memory arrangement schemes, our design can achieve an encoding rate of up to 270 Mbps with very limited hardware overhead. Meanwhile, we also describe techniques to effectively test the manufacture faults in chip implementation. Experimental results exhibit the advantages of employing the developed design and test schemes.
Description Author affiliation: Nat. Cheng-Kung Univ., Tainan (Chia-Cheng Lo; Ying-Jhong Zeng; Ming-Der Shieh)
ISBN 9781424412716
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2007-10-30
Publisher Place Taiwan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 254.84 kB
Page Count 4
Starting Page 1
Ending Page 4


Source: IEEE Xplore Digital Library