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Author Chatterjee, D. ♦ Koyfman, A. ♦ Morad, R. ♦ Ziv, A. ♦ Bertacco, V.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2012
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Registers ♦ Acceleration ♦ Software ♦ Microprocessors ♦ Hardware ♦ Vectors ♦ Checking on Acceleration ♦ Simulation Acceleration ♦ Checking
Abstract Simulation-based verification is an integral part of a modern microprocessor's design effort. Commonly, several checking techniques are deployed alongside the simulator to detect and localize each functional bug manifestation. Among these, a widespread technique entails comparing a microprocessor design's outputs with a golden model at the architectural granularity, instruction-by-instruction. However, due to exponential growth in design complexity, the performance of software-based simulation falls far short of achieving an acceptable level of coverage, which typically requires billions of simulation cycles. Hence, verification engineers rely on simulation acceleration platforms. Unfortunately, the intrinsic characteristics of these platforms make the adoption of the checking solutions mentioned above a challenging goal: for instance, the lockstep execution of a software checker together with the design's simulation is no longer feasible. To address this challenge we propose an innovative solution for instruction-by-instruction (IBI) checking tailored to acceleration platforms. We provide novel design techniques to decouple event tracing from checking by including specialized tracing logic and by adding a post-simulation checking phase. Note that simulation performance in acceleration platforms degrades when increasing the number of signals that are traced; hence, it is imperative to generate a compact summary of the information required for checking, collecting and tracing only a few bits of information per cycle.
Description Author affiliation: IBM Res. Lab., Haifa, Israel (Koyfman, A.; Morad, R.; Ziv, A.) || Univ. of Michigan Ann Arbor, Ann Arbor, MI, USA (Chatterjee, D.; Bertacco, V.)
ISBN 9781450311991
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2012-06-03
Publisher Place USA
Rights Holder Association for Computing Machinery, Inc. (ACM)
e-ISBN 9781450311991
Size (in Bytes) 633.24 kB
Page Count 7
Starting Page 955
Ending Page 961

Source: IEEE Xplore Digital Library