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Author Ercanli, E. ♦ Papachristou, C.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1996
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Registers ♦ Processor scheduling ♦ Application specific processors ♦ Application software ♦ VLIW ♦ Design automation ♦ Computer architecture ♦ Permission ♦ Coprocessors ♦ Logic
Abstract We outline general design steps of our synthesis tool to realize application specific co-processors such that for a given scientific application having intensive iterative computations especially with recurrences, a VLIW type of co-processor is synthesized and realized, and an accompanying parallel code is generated. We introduce a novel register file model, Shifting Register File (SRF), based on cyclic regularity of register file accesses; and a simple method, Expansion Scheduling, for scheduling iterative computations, which is based on cyclic regularity of loops. We also present a variable-register file allocation method and show how simple logic units can be used to activate proper registers at run time through an example.
Description Author affiliation: Dept. of Comput. Eng., Case Western Reserve Univ., Cleveland, OH, USA (Ercanli, E.)
ISBN 0780332946
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1996-06-03
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 700.90 kB
Page Count 6
Starting Page 35
Ending Page 40


Source: IEEE Xplore Digital Library