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Author Lacrampe, N. ♦ Alaeldine, A. ♦ Caignet, F. ♦ Perdriau, R.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2007
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics
Subject Keyword Electrostatic discharge ♦ Integrated circuit modeling ♦ Semiconductor device modeling ♦ Circuit testing ♦ Integrated circuit testing ♦ Power system transients ♦ Electrostatic measurements ♦ Transmission line measurements ♦ Stress measurement ♦ Integrated circuit measurements
Abstract This paper presents a measurement methodology aimed at predicting the susceptibility of integrated circuits against electrostatic discharge (ESD) stresses. In our application, a very fast transmission line pulsing (VF-TLP) test bench is used to inject a disturbance into an IC under operation. For simulation purposes, each part of the test bench is modeled separately, and these models are assembled in order to obtain a complete model representing both the injection set-up and the IC itself. The suggested injection model is validated thanks to correlations between measurements and simulations on a full- custom 0.18 mum CMOS IC.
Description Author affiliation: Univ. de Toulouse, Toulouse (Lacrampe, N.)
ISBN 1424413494
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2007-07-09
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 475.78 kB
Page Count 5
Starting Page 1
Ending Page 5


Source: IEEE Xplore Digital Library