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Author Karp, J. ♦ Fakhruddin, M. ♦ Hart, M. ♦ Li, R. ♦ Fu-Hing Ho ♦ Reilly, S. ♦ Tan, P. ♦ Tsaggaris, D. ♦ Pai, S.Y.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2011
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics
Subject Keyword Electrostatic discharge ♦ MOS devices ♦ Stress ♦ Discharges ♦ Resistors ♦ Substrates
Abstract A small footprint ESD protection scheme is developed for the hot-swappable chip interface (I/O). Elimination of ESD elements in the I/O to VCCO path, and elimination of ESD elements for LVDS drivers has enabled ∼50% ESD area reduction. The design is qualified for production and has passed ESD specifications of 2000V HBM, 500V CDM, and 200V MM with excellent margin.
Description Author affiliation: Xilinx Inc., 2100 Logic Drive, San Jose, California, 95124, USA (Karp, J.; Fakhruddin, M.; Hart, M.; Li, R.; Fu-Hing Ho; Reilly, S.; Tan, P.; Tsaggaris, D.; Pai, S.Y.)
ISBN 9781585371938
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2011-09-11
Publisher Place USA
Rights Holder EOS/ESD Association, Inc.
Size (in Bytes) 1.96 MB
Page Count 6
Starting Page 1
Ending Page 6

Source: IEEE Xplore Digital Library