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Author Corno, F. ♦ Cumani, G. ♦ Sonza Reorda, M. ♦ Squillero, G.
Sponsorship IEEE Comput. Soc. Test Technol. Tech. Council
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2001
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Automatic test pattern generation ♦ Circuit faults ♦ Application specific integrated circuits ♦ Test pattern generators ♦ Logic testing ♦ Circuit testing ♦ Circuit simulation ♦ Integrated circuit manufacture ♦ Integrated circuit technology ♦ Moore's Law
Abstract The ASIC design flow is rapidly moving towards higher description levels, and most design activities are now performed at the RT-level. However, test-related activities are lacking behind this trend, mainly since effective fault models and test pattern generation tools are still missing. This paper proposes techniques for implementing a high-level ATPG. The proposed algorithm mixes a code coverage-oriented approach with fault-oriented optimizations. Moreover, it exploits a fault model at the RT-level that enables efficient fault simulation and guarantees good correlation with gate-level fault coverage. Experimental results show that the achieved results are comparable or better than those obtained at the gate level or by similar RT-level approaches.
Description Author affiliation: Dipt. di Automatica e Informatica, Politecnico di Torino, Italy (Corno, F.)
ISBN 0769513786
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2001-11-19
Publisher Place Japan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 537.30 kB
Page Count 6
Starting Page 225
Ending Page 230


Source: IEEE Xplore Digital Library