Access Restriction

Author Schneider, C.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1999
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Data structures ♦ Decoding ♦ Electronic mail ♦ Clocks ♦ Timing ♦ Logic ♦ Space exploration ♦ Performance evaluation ♦ MPEG standards ♦ Java
Abstract A VHDL-based methodology for top-down design, starting from an executable specification, supporting refinement towards RTL is proposed for the multimedia domain. The methodology is demonstrated using an MPEG-2 video decoder. A key idea for writing an initial executable specification is to keep the modeling style as close as possible to thinking in the domain. The executable specification is refined by partitioning the initially sequential model into concurrent processes and by moving functionality between blocks. During partitioning, control-dominated parts are separated from data-intensive calculations to enable domain-specific refinement. Finally the timing is refined from the causal to the clock-related level to enable performance simulation.
Description Author affiliation: Corp. Res., Infineon Technol., Munich, Germany (Schneider, C.)
ISBN 0769503217
ISSN 10896503
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1999-09-08
Publisher Place Italy
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 24.26 kB
Page Count 4
Starting Page 394
Ending Page 397

Source: IEEE Xplore Digital Library