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Author Kelley, K. ♦ Wachs, M. ♦ Stevenson, J. ♦ Richardson, S. ♦ Horowitz, M.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2012
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Algorithm design and analysis ♦ Decoding ♦ Optimization ♦ Timing ♦ Reachability analysis ♦ Standards ♦ Logic gates ♦ Flexibility ♦ Reachability ♦ Synthesis ♦ HDL
Abstract Hardware modules would be much easier to reuse if they supported generic flexible high-level interfaces. However, these interfaces are rarely used since they lead to timing and area overheads compared to a customized design. This paper describes a reachability analysis framework that identifies over-provisioning in instances of flexible design, and offers a technique for annotating this information so that modern synthesis tools can remove most of the overhead. Results are demonstrated on a variety of flexible structures, including functional blocks, programmable state machines, and latency-insensitive interfaces.
ISBN 9781450311991
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2012-06-03
Publisher Place USA
Rights Holder Association for Computing Machinery, Inc. (ACM)
e-ISBN 9781450311991
Size (in Bytes) 347.89 kB
Page Count 7
Starting Page 783
Ending Page 789

Source: IEEE Xplore Digital Library