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Author Chi-Un Lei ♦ Ngai Wong
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2006
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Polynomials ♦ Very large scale integration ♦ Hardware ♦ Digital filters ♦ Feedback ♦ Delay ♦ Noise reduction ♦ Transfer functions ♦ Costs ♦ Equations
Abstract An improved multiplierless digital filter in transposed direct form II (DFIIt) structure is proposed for efficient VLSI implementation. The traditional delay operator is replaced with standardized polynomial operator. Coefficient scaling is implemented using canonical signed digit (CSD) and subexpression sharing. The proposed structure minimizes roundoff noise gain and further reduces hardware complexity
Description Author affiliation: Dept. of Electr. & Electron. Eng., Hong Kong Univ. (Chi-Un Lei; Ngai Wong)
ISBN 1424405483
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2006-11-14
Publisher Place China
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 3.51 MB
Page Count 4
Starting Page 1
Ending Page 4


Source: IEEE Xplore Digital Library