Thumbnail
Access Restriction
Subscribed

Author Nguyen, H.N. ♦ Tual, J.P. ♦ Ducousso, L. ♦ Thill, M. ♦ Vallet, P.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1994
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Logic design ♦ Central Processing Unit ♦ CMOS logic circuits ♦ Design methodology ♦ Circuit synthesis ♦ Hardware ♦ Logic circuits ♦ Signal synthesis ♦ Timing ♦ Application software
Abstract This paper describes the large scale application of logic synthesis and formal verification using the BONSAI system to the design of the CPU and caches of a high-end mainframe system. The key feature of this application is the methodology that integrates a set of logic synthesis and formal verification techniques to build an effective logic-design system to support the design of high-performance, high-density circuits.<<ETX>>
Description Author affiliation: Dept. of Design Methodology, BULL SA, Les Clayes-sous-Bois, France (Nguyen, H.N.; Tual, J.P.)
ISBN 0818654104
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1994-02-28
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 483.70 kB
Page Count 5
Starting Page 60
Ending Page 64


Source: IEEE Xplore Digital Library