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Author Wunderlich, H.-J.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1987
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Circuit testing ♦ Circuit faults ♦ Automatic testing ♦ Fault detection ♦ Electrical fault detection ♦ Permission ♦ Test pattern generators ♦ Circuit simulation ♦ Costs ♦ Upper bound ♦ fault simulation ♦ Optimized random test ♦ self test ♦ fault detection probabilities
Abstract Self testing of integrated circuits by random patterns has several technical and economical advantages. But there exists a large number of circuits which cannot be randomly tested, since the fault coverage achieved that way would be too low. In this paper we show that this problem can be solved by unequiprobable random patterns, and an efficient procedure is presented computing the specific optimal probability for each primary input of a combinational network. Those optimized random patterns can be produced on the chip during self test or off the chip in order to accelerate fault simulation and test pattern generation.
Description Author affiliation: Universitat Karlsruhe Institut fur Informatik, Karlsruhe, FRG (Wunderlich, H.-J.)
ISBN 0818607815
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1987-06-28
Publisher Place USA
Rights Holder Association for Computing Machinery, Inc. (ACM)
Size (in Bytes) 649.60 kB
Page Count 7
Starting Page 392
Ending Page 398

Source: IEEE Xplore Digital Library