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Author Lee, S.J. ♦ Lee, C.H. ♦ Kim, Y.H. ♦ Luan, H.F. ♦ Bai, W.P. ♦ Jeon, T.S. ♦ Kwong, D.L.
Sponsorship JSAP: Japan Soc. Appl. Phys.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2001
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Hafnium oxide ♦ High K dielectric materials ♦ High-K gate dielectrics ♦ Conducting materials ♦ CMOS technology ♦ Electrodes ♦ Inorganic materials ♦ Fabrication ♦ CMOS process ♦ Robustness
Abstract In this paper, the materials and processing challenges for the fabrication of high-quality, ultra-thin (EOT<1 nm) dual-poly high-k gate stack for sub-100 nm CMOS technology are reviewed along with recent results on CVD HfO/sub 2/. The requirement for ultra thin and robust interface layers to avoid any thickness increase due to post-deposition processing to achieve the thinnest possible EOT (equivalent oxide thickness) is discussed. Results are presented on the thermal stability of high-k materials, and interfacial reactions of high-k/Si and high-k/gate electrode interfaces. We also discuss key factors that govern the conduction and degradation mechanisms in high-k gate stacks. Finally, recent work on metal nitrides as possible gate electrode materials is reviewed and the upper thermal budget limit for such materials is discussed.
Description Author affiliation: Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA (Lee, S.J.)
ISBN 4891140216
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2001-11-01
Publisher Place Japan
Rights Holder Japan Soc of Applied Physics
Size (in Bytes) 483.44 kB
Page Count 6
Starting Page 80
Ending Page 85

Source: IEEE Xplore Digital Library