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Author Junho Lee ♦ Hyunseok Kim ♦ Kimyung Kyung ♦ Minyoung You ♦ Hyungdong Lee ♦ Kunwoo Park ♦ Byongtae Chung
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2007
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics
Subject Keyword Design optimization ♦ Voltage ♦ Capacitors ♦ Packaging ♦ Semiconductor device noise ♦ Noise generators ♦ Random access memory ♦ Noise reduction ♦ Impedance ♦ Process design
Abstract In this paper, design procedure and analysis method of power delivery network of DDR2 memory chip are introduced. The power delivery network of memory chip is optimized by tuning the location of power/ground chip pad and on-chip decoupling capacitor's W/L size. The results show that the properly designed power/ground chip pads and decoupling capacitors greatly reduce power noise, resulting in the reduction of chip cost by using less area for on-chip decoupling capacitor.
Description Author affiliation: Hynix Semicond. Inc., Icheon (Junho Lee; Hyunseok Kim; Kimyung Kyung; Minyoung You; Hyungdong Lee; Kunwoo Park; Byongtae Chung)
ISBN 9781424408832
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2007-10-29
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 1.78 MB
Page Count 4
Starting Page 87
Ending Page 90

Source: IEEE Xplore Digital Library