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Author Shinogi, T. ♦ Yamada, H. ♦ Hayashi, T. ♦ Tsuruoka, S. ♦ Yoshikawa, T.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2005
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Costs ♦ Circuit testing ♦ Electronic equipment testing ♦ Flip-flops ♦ Large scale integration ♦ Data engineering ♦ Hardware ♦ Circuit faults ♦ Computer architecture ♦ Electronic mail
Abstract To reduce the test application time and the test data volume in full-scan testing, various methods are proposed which utilize some additional built-in circuits dedicated for testing. In contrast, a previous method, called Reduced Scan Shift, does not utilize any additional built-in hardware. However, the method relies on scan chain flip-flop reordering, which is not always applicable. In this paper, we propose a test data sequence generation method for Reduced Scan Shift without scan chain flip-flop reordering. Our method fully utilizes justification technique and don't-care bits in test vectors.
Description Author affiliation: Mie University, Tsu, Mie, JAPAN (Shinogi, T.)
ISBN 0769524818
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2005-12-18
Publisher Place India
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 170.70 kB
Page Count 6
Starting Page 366
Ending Page 371


Source: IEEE Xplore Digital Library