Access Restriction

Author Helbig, J.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1995
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Timing ♦ System-level design ♦ Control system synthesis ♦ Switches ♦ Memory architecture ♦ Automatic logic units
Abstract Statecharts can complement VHDL, in particular for system level design. We present what would be needed to extend VHDL by state based specification, sharing its syntax and the fundamental notion of time. The resulting integration is very tight, allowing, by comparison to existing approaches, more precise control for synthesis, incorporation of library components, multiple statechart instantiations and smooth paradigm switches. The language is being developed and implemented in the ESPRIT project FORMAT, and has been successfully employed for formal verification against timing diagram specifications.
Description Author affiliation: Oldenburg Univ., Germany (Helbig, J.)
ISBN 4930813670
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1995-08-29
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 1.06 MB
Page Count 10
Starting Page 675
Ending Page 684

Source: IEEE Xplore Digital Library