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Author Boule, M. ♦ Zilic, Z.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2007
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Emulation ♦ Fusion power generation ♦ Circuit synthesis ♦ Automata ♦ Circuit simulation ♦ Hardware design languages ♦ Pattern matching ♦ Encoding ♦ Specification languages ♦ Monitoring
Abstract In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used assertion-based verification (ABV) languages. A checker generator capable of transforming assertions into efficient circuits allows the adoption of ABV in hardware emulation. Towards that goal, we introduce the algorithms for sequence fusion and length matching intersection, two SERE operators that are not typically used over regular expressions. We also develop an algorithm for generating failure detection automata, a concept critical to extending regular expressions for ABV, as well as present our efficient symbol encoding. Experiments with complex sequences show that our tool outperforms the best known checker generator.
Description Author affiliation: McGill Univ., Montreal, Que. (Boule, M.; Zilic, Z.)
ISBN 1424406293
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2007-01-23
Publisher Place Japan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 179.07 kB
Page Count 6
Starting Page 324
Ending Page 329

Source: IEEE Xplore Digital Library