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Author Wei-Jin Dai ♦ Huang, D. ♦ Chin-Chih Chang ♦ Courtoy, M.
Sponsorship IEEE Circuits & Syst. Soc. ♦ ACM SIGDA ♦ IEICE (Inst. Electon., Inf. & Commun. Eng.) ♦ IPSJ (Inf. Process. Soc. Japan)
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2003
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Silicon ♦ Virtual prototyping ♦ Chip scale packaging ♦ Timing ♦ Design methodology ♦ Prototypes ♦ Process design ♦ Logic design ♦ Routing ♦ System-on-a-chip
Abstract A design methodology for the implementation of multi-million gate system-on-chip designs is described. The new methodology is based on the creation of a silicon virtual prototype early in the back-end design process. The prototype is generated in a fraction of the time required to complete the traditional back-end flow but still maintains very high correlation with the final design. The physical prototype becomes the 'cockpit' where many design implementation decisions can be optimized by leveraging the short iteration times. Hierarchical design methodologies benefit from the prototyping stage by enabling a more optimal partitioning. The silicon virtual prototype also alters the nature of the hand-off model between front-end and back-end designers. The netlist can now be quickly validated using the prototype: the physical reality is being injected early in the design process resulting in fewer iterations between front-end and back-end.
Description Author affiliation: Cadence Design Syst. Inc., San Jose, CA, USA (Wei-Jin Dai; Huang, D.; Chin-Chih Chang; Courtoy, M.)
ISBN 0780376595
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2003-01-24
Publisher Place Japan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 542.08 kB
Page Count 5
Starting Page 635
Ending Page 639


Source: IEEE Xplore Digital Library