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Author De Micheli, G. ♦ Seiculescu, C. ♦ Murali, S. ♦ Benini, L. ♦ Angiolini, F. ♦ Pullini, A.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2010
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Network-on-a-chip ♦ Delay estimation ♦ System-on-a-chip ♦ Communication system traffic control ♦ Power system interconnection ♦ Energy consumption ♦ Timing ♦ Wires ♦ System performance ♦ Field programmable gate arrays ♦ SoC ♦ Network on Chip ♦ NoC ♦ System on Chip
Abstract Research on Networks on Chips (NoCs) has spanned over a decade and its results are now visible in some products. Thus the seminal idea of using networking technology to address the chip-level interconnect problem has been shown to be correct. Moreover, as technology scales down in geometry and chips scale up in complexity, NoCs become the essential element to achieve the desired levels of performance and quality of service while curbing power consumption levels. Design and timing closure can only be achieved by a sophisticated set of tools that address NoC synthesis, optimization and validation.
Description Author affiliation: DEIS, University of Bologna (Benini, L.) || LSI, EPFL, Lausanne, Switzerland (De Micheli, G.; Seiculescu, C.) || iNoCs, Lausanne, Switzerland (Murali, S.; Angiolini, F.; Pullini, A.)
ISBN 9781424466771
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2010-06-13
Publisher Place USA
Rights Holder Association for Computing Machinery, Inc. (ACM)
e-ISBN 9781450300025
Size (in Bytes) 547.58 kB
Page Count 6
Starting Page 300
Ending Page 305


Source: IEEE Xplore Digital Library