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Author Yilmaz, M. ♦ Hower, D.R. ♦ Ozev, S. ♦ Sorin, D.J.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2006
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Microprocessors ♦ Fault tolerance ♦ Circuit faults ♦ Energy consumption ♦ Hardware ♦ Performance analysis ♦ Security ♦ Contracts ♦ Failure analysis ♦ Fault detection
Abstract In this paper, we propose a low-cost fault tolerance technique for microprocessor multipliers, both non-pipelined (NP) and pipelined (P). Our fault tolerant multiplier designs are capable of detecting and correcting errors, diagnosing hard faults, and reconfiguring to take the faulty sub-unit off-line. We utilize the branch misprediction recovery mechanism in the microprocessor core to take the error detection process off the critical path. Our analysis shows that our scheme provides 99% fault security and, compared to a baseline unprotected multiplier, achieves this fault tolerance with low performance overhead (5% for NP and 2.5% for P multiplier) and reasonably low area (38% NP and 26% P) and power consumption (36% NP and 28.5% P) overheads
Description Author affiliation: Dept. of Electr. & Comput. Eng., Duke Univ., Durham, NC (Yilmaz, M.; Hower, D.R.; Ozev, S.; Sorin, D.J.)
ISBN 1424402913
ISSN 10893539
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2006-10-22
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 369.64 kB
Page Count 10
Starting Page 1
Ending Page 10


Source: IEEE Xplore Digital Library