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Author Hsing-Chung Liang ♦ Chung Len Lee ♦ Chen, J.E.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1996
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Circuit testing ♦ Sequential circuits ♦ Sequential analysis ♦ Circuit faults ♦ Benchmark testing ♦ Flip-flops ♦ Test pattern generators ♦ Electrical fault detection ♦ Fault detection ♦ Degradation
Abstract For sequential circuit test pattern generation, the information on invalid states will help greatly on backward justification to reduce the test generation time. This paper proposes three algorithms to find invalid states for sequential circuit test generation. The first two algorithms search the complete set of invalid states by exploring all valid states and reachable states respectively. The first algorithm is efficient for circuits having more invalid states than valid states while the second algorithm is efficient for circuits having more valid states than invalid states. The third algorithm searches only the invalid states that are required for test generation to stop justification early. Experimental results on ISCAS benchmark circuits show that the algorithm can identify invalid states in short time and can help improve test generation significantly in the fault coverage, detection efficiency, and generation time.
Description Author affiliation: Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan (Hsing-Chung Liang)
ISBN 0818674784
ISSN 10857735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1996-11-20
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 539.14 kB
Page Count 6
Starting Page 10
Ending Page 15

Source: IEEE Xplore Digital Library