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Author Ould Bachir, T. ♦ Sawan, M. ♦ Brault, J.-J.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2008
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science ♦ Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics
Subject Keyword Hardware ♦ Sampling methods ♦ Exponential distribution ♦ Field programmable gate arrays ♦ Computer architecture ♦ Acceleration ♦ High performance computing ♦ Decision trees ♦ Testing ♦ Random number generation ♦ random number generation ♦ Sampling methods ♦ exponential distribution
Abstract Hardware acceleration in high performance computing context is of growing interest, particularly in the field of Monte Carlo methods where the resort to FPGA technology enhances execution speed by several orders. For this purpose, a particular attention has been given lately to hardware-based non-uniform random variate generators. In this paper we present both a hardware-dedicated decision tree technique for the generation of exponential variates and a derived architecture implemented in FPGA. The proposed design passes the $chi^{2}$ test with a p-value of 0.5499 and ensures absence of serial correlation. The exponential random number generator reaches 375 MHz on a Xilinx Virtex II Pro FPGA and occupies about 3 % of the available space.
Description Author affiliation: Dept. of Electr. Eng. Montreal, Ecole Polytech. de Montreal, Montreal, QC, Canada (Ould Bachir, T.; Sawan, M.; Brault, J.-J.)
ISBN 9781424416424
ISSN 08407789
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2008-05-04
Publisher Place Canada
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 230.14 kB
Page Count 4
Starting Page 001393
Ending Page 001396

Source: IEEE Xplore Digital Library