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Author Dejhan, K. ♦ Tooprakai, P. ♦ Mitatha, S. ♦ Cheevasuvit, F. ♦ Soonyeekan, C.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2000
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword BiCMOS integrated circuits ♦ Latches ♦ Power dissipation ♦ Inverters ♦ Circuit simulation ♦ Delay ♦ Feedback loop ♦ Semiconductor device modeling ♦ Bipolar transistors ♦ Design optimization
Abstract This paper proposes a method to design both CMOS and BiCMOS latches by determining three constraints: the circuit power dissipation, the circuit area and the circuit speed. Meta-stable operation is observed by considering all three constraints. All simulation results have been produced based on the 0.8 /spl mu/m design rule using the PSPICE simulator program.
Description Author affiliation: Fac. of Eng., King Mongkut's Inst. of Technol., Bangkok, Thailand (Dejhan, K.)
ISBN 0780364309
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2000-11-13
Publisher Place Malaysia
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 309.10 kB
Page Count 5
Starting Page 152
Ending Page 156

Source: IEEE Xplore Digital Library