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Author Ouzounov, S. ♦ Roza, E. ♦ Hegt, H. ♦ van der Weide, G. ♦ van Roermund, A.
Sponsorship IEEE Solid-State Circuits Soc
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2004
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Delta-sigma modulation ♦ Delta modulation ♦ Hysteresis ♦ Limit-cycles ♦ Variable speed drives ♦ Frequency ♦ Equations ♦ Laboratories ♦ Feedback circuits ♦ Space vector pulse width modulation
Abstract This work describes the design of asynchronous sigma delta modulators (ASDMs) with a binary quantizer with hysteresis. The ASDM is treated as a closed loop non-linear system that operates using an inherent limit cycle. A first and a second order ASDM have been implemented in a digital 0.18 /spl mu/m CMOS technology. The measured SFDR is 75 dB in a frequency band of 8 MHz for the first-order and 72 dB in a band of 12 MHz for the second-order ASDM.
Description Author affiliation: Eindhoven Univ. of Technol., Netherlands (Ouzounov, S.)
ISBN 0780384954
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2004-10-06
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 407.14 kB
Page Count 4
Starting Page 181
Ending Page 184

Source: IEEE Xplore Digital Library