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Author Moonen, A. ♦ Bekooij, M. ♦ van den Berg, R. ♦ van Meerbergen, J.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2008
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Multiprocessing systems ♦ Delay ♦ Buffer storage ♦ Algorithm design and analysis ♦ Streaming media ♦ Digital Radio Mondiale ♦ Receivers ♦ Prefetching ♦ Memory management ♦ Power system modeling
Abstract Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor system- on-chip. An external memory that is shared between processors is a bottleneck in current and future systems. Cache misses and a large cache miss penalty contribute to a low processor utilisation. In this paper, we describe a novel cache optimisation technique to reduce instruction and data cache misses for streaming applications. The instruction and data locality are improved by executing a task multiple times before moving to the next task. Furthermore, we introduce a dataflow model that is used to trade-off the number of cache misses against end-to-end latency and memory usage. For our industrial application, which is a Digital Radio Mondiale receiver, the number of cache misses is reduced with a factor 4.2.
Description Author affiliation: Univ. of Technol. Eindhoven, Eindhoven (Moonen, A.)
ISBN 9783981080131
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2008-03-10
Publisher Place Germany
Rights Holder European Design Automation Association (EDAA)
Size (in Bytes) 460.74 kB
Page Count 6
Starting Page 300
Ending Page 305

Source: IEEE Xplore Digital Library