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Author Qiang Zhu ♦ Shrivastava, A. ♦ Dutt, N.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2007
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Timing ♦ Pipelines ♦ Hazards ♦ Registers ♦ Automatic testing ♦ Computer science ♦ Embedded system ♦ Radio frequency ♦ Fault detection ♦ Delay
Abstract Customizing the bypasses in pipelined processors is an effective and popular means to perform power, performance and complexity trade-offs in embedded systems. However existing techniques are unable to automatically generate test patterns to functionally validate a partially bypassed processor. Manually specifying directed test sequences to validate a partially bypassed processor is not only a complex and cumbersome task, but is also highly error-prone. In this paper we present an automatic directed test generation technique to verify a partially bypassed processor pipeline using a high-level processor description. We define a fault model and coverage metric for a partially bypassed processor pipeline and demonstrate that our technique can fully cover all the faults using 107,074 tests for the Intel XScale processor within 40 minutes. In contrast, randomly generated tests can achieve 100% coverage with 2 million tests after half day. Furthermore, we demonstrate that our technique is able to generate tests for all possible bypass configurations of the Intel XScale processor
Description Author affiliation: Fujitsu Labs. LTD., Kawasaki (Qiang Zhu)
ISBN 9783981080124
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2007-04-16
Publisher Place France
Rights Holder ESCI
Size (in Bytes) 308.19 kB
Page Count 6
Starting Page 1
Ending Page 6


Source: IEEE Xplore Digital Library