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Author Tsai-Ying Lin ♦ Tsung-Han Lin ♦ Hui-Hsiang Tung ♦ Rung-Bin Lin
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2007
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Libraries ♦ Routing ♦ Wires ♦ Pins ♦ Costs ♦ Computer science ♦ Design engineering ♦ Computer aided manufacturing ♦ Standards development ♦ Bipartite graph
Abstract Double-via placement is important for increasing chip manufacturing yield. Commercial tools and recent work have done a great job for it. However, they are found with a limited capability of placing more double vias (called vial) between metal 1 and metal 2. Such a limitation is caused by the way we design the standard cells and can not be resolved by developing better tools. This paper presents a double-via-driven standard cell library design approach to solving this problem. Compared to the results obtained using a commercial cell library, our library on average achieves 78% reduction in dead vias and 95% reduction in dead vials at the expense of 11% increase in total via count. We achieve these results (almost) at no extra cost in total cell area and wire length
Description Author affiliation: Dept. of Comput. Sci. & Eng., Yuan Ze Univ., Chung-Li (Tsai-Ying Lin)
ISBN 9783981080124
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2007-04-16
Publisher Place France
Rights Holder ESCI
Size (in Bytes) 413.32 kB
Page Count 6
Starting Page 1
Ending Page 6


Source: IEEE Xplore Digital Library