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Author Kuen-Yu Tsai ♦ Wei-Jhih Hsieh ♦ Yuan-Ching Lu ♦ Bo-Sen Chang ♦ Sheng-Wei Chien ♦ Yi-Chang Lu
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2010
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Lithography ♦ Integrated circuit interconnections ♦ Circuit simulation ♦ Pattern matching ♦ Table lookup ♦ Libraries ♦ Shape measurement ♦ Circuit testing ♦ Large-scale systems ♦ Optical distortion
Abstract Modern nanometer integrated circuits are patterned by sub-wavelength lithography with significant shape deviation from drawn layouts. Full-chip parasitics extraction faces new challenges since shape distortions such as line end rounding and corner rounding cannot be accurately characterized by existing layout parameter extraction (LPE) techniques which assume perfect polygons. A new LPE method and efficient shape approximation algorithms are proposed to account for the shape distortions. Preliminary results verified by field solver simulations indicate that accuracy of parasitics extraction can be significantly improved.
Description Author affiliation: Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan (Kuen-Yu Tsai; Wei-Jhih Hsieh; Yuan-Ching Lu; Bo-Sen Chang; Sheng-Wei Chien; Yi-Chang Lu)
ISBN 9781424457656
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2010-01-18
Publisher Place Taiwan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 639.34 kB
Page Count 6
Starting Page 651
Ending Page 656

Source: IEEE Xplore Digital Library