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Author Jilong Kuang ♦ Bhuyan, L.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2010
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Delay ♦ Throughput ♦ Pipeline processing ♦ Parallel processing ♦ Multicore processing ♦ Scheduling algorithm ♦ Algorithm design and analysis ♦ Uniform resource locators ♦ Protocols ♦ Computer science ♦ multicore architecture ♦ Parallel-pipelining ♦ packet processing
Abstract Current packet processing systems only aim at producing high throughput without considering packet latency reduction. For many real-time embedded network applications, it is essential that the processing time not exceed a given threshold. In this paper, we propose LATA, a LAtency and Throughput-Aware packet processing system for multicore architectures. Based on parallel pipeline core topology, LATA can satisfy the latency constraint and produce high throughput by exploiting fine-grained task-level parallelism. We implement LATA on an Intel machine with two Quad-Core Xeon E5335 processors and compare it with four other systems (Parallel, Greedy, Random and Bipar) for six network applications. LATA exhibits an average of 36.5% reduction of latency and a maximum of 62.2% reduction of latency for URL over Random with comparable throughput performance.
Description Author affiliation: Computer Science & Engineering Department Unviersity of California, Riverside 900 University Ave, Riverside, CA 92521, USA (Jilong Kuang; Bhuyan, L.)
ISBN 9781424466771
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2010-06-13
Publisher Place USA
Rights Holder Association for Computing Machinery, Inc. (ACM)
e-ISBN 9781450300025
Size (in Bytes) 517.44 kB
Page Count 6
Starting Page 36
Ending Page 41

Source: IEEE Xplore Digital Library