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Author Sakakura, M. ♦ Fukazawa, Y.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1994
Language English
Subject Domain (in DDC) Computer science, information & general works ♦ Data processing & computer science
Subject Keyword Acceleration ♦ Circuit simulation ♦ Logic circuits ♦ Logic design ♦ Computational modeling ♦ Informatics ♦ Marine vehicles ♦ Predictive models ♦ Discrete event simulation ♦ Computer science
Abstract We present a method for acceleration of logic simulations. The logic simulation is mainly used to detect malfunctions in the logical design phase. As the size of logical circuits grows, acceleration of the logic simulation becomes increasingly required. Several acceleration methods have been presented for this purpose. The outstanding feature of our method is that it accelerates the simulation speed in accordance with the dynamic behaviours of target circuits. A global dynamic behaviour is predicted to realize this feature, through the investigation of the relationship among gates in the early stage of the simulation. Using the relationships, a logic simulation is accelerated by a process called "grouping". We have confirmed that the dynamic information of the circuits accelerates logical simulation by the evaluation system.
Description Author affiliation: Centre for Inf., Waseda Univ., Tokyo, Japan (Sakakura, M.)
ISBN 0780318625
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1994-08-22
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 318.44 kB
Page Count 4
Starting Page 828
Ending Page 831


Source: IEEE Xplore Digital Library