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Author Cai, H. ♦ Hegge, J.J.A.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1988
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Partitioning algorithms ♦ Simulated annealing ♦ Shape ♦ Clustering algorithms ♦ Algorithm design and analysis ♦ Network theory (graphs) ♦ Circuit simulation ♦ Very large scale integration ♦ Merging ♦ Analytical models
Abstract Four floorplanning algorithms for full-custom ICs are compared. They are the min-cut algorithm, the force-directed algorithm, simulated annealing, and the sequence heuristic. Experimental results are shown. The discussion is restricted to the class of floorplans with a slicing structure. Experimental results are shown.<<ETX>>
Description Author affiliation: Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands (Cai, H.; Hegge, J.J.A.)
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1988-05-16
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 341.02 kB


Source: IEEE Xplore Digital Library