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Author Tamiya, Y.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1996
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Delay estimation ♦ Circuit synthesis ♦ Libraries ♦ Design optimization ♦ Delay effects ♦ Equations ♦ Laboratories ♦ Combinational circuits ♦ Large scale integration ♦ Phase measurement
Abstract This paper proposes path mapping, a method of delay estimation for technology independent combinational circuits. Path mapping provides fast and accurate delay estimation using the common ideas of tree covering technology mapping. First, path mapping performs technology mapping for all paths in the circuit with minimum delay. Then, it finds the most critical path among all the paths in the circuit. Finally, it answers its path delay as the circuit delay. Experimental results show path mapping estimates more accurate circuit delay than unit delay, and runs much faster than the technology mapper.
Description Author affiliation: Fujitsu Labs. Ltd., Kawasaki, Japan (Tamiya, Y.)
ISBN 0780336623
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1997-01-28
Publisher Place Japan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 530.76 kB
Page Count 6
Starting Page 31
Ending Page 36

Source: IEEE Xplore Digital Library