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Author Barrena, J.A. ♦ Aurtenechea, S. ♦ Canales, J.M. ♦ Rodriguez, M.A. ♦ Marroyo, L.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2005
Language English
Subject Domain (in DDC) Natural sciences & mathematics ♦ Physics ♦ Electricity & electronics ♦ Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Algorithm design and analysis ♦ Irrigation ♦ Static Synchronous Compensator (STATCOM) ♦ Multilevel Converters ♦ Capacitors ♦ Flexible AC transmission systems ♦ Pulse width modulation ♦ Distribution of electrical energy ♦ Pulse width modulation inverters ♦ Reactive power control ♦ Circuit topology ♦ Filters ♦ Voltage Source Inverters (VSI ♦ Automatic voltage control ♦ FACTS
Abstract The aim of this paper is to present a design method of two different DSTATCOM multilevel topologies which are suitable to be used connected to the distribution grid. These devices have been classically commutated at fundamental line-frequencies, but the evolution of power semiconductors has allowed to increase switching frequencies and the power ratings of these devices, permitting the use of PWM modulation techniques. This paper mainly focuses the design issues of the NPC and cascaded H-bridge multilevel topologies for DSTATCOM applications, presenting a method for the dimensioning of the different elements that compose the device, paying special attention to the DC bus capacitor sizing and output filter inductance sizing
Description Author affiliation: Escuela Politecnica Superior, Universidad de Mondragon (Barrena, J.A.; Aurtenechea, S.; Canales, J.M.; Rodriguez, M.A.)
ISBN 9075815093
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2005-09-11
Publisher Place Germany
Rights Holder EPE Association
Size (in Bytes) 1.65 MB

Source: IEEE Xplore Digital Library