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Author Bing-Yang Lin ♦ Mincent Lee ♦ Cheng-Wen Wu
Sponsorship IEEE Comput. Soc.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2013
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Redundancy ♦ Maintenance engineering ♦ Memory architecture ♦ Three-dimensional displays ♦ Memory management ♦ Random access memory ♦ Algorithm design and analysis ♦ yield improvement ♦ memory built-in self-repair (BISR) ♦ memory testing ♦ redundancy analysis (RA) ♦ redundancy repair ♦ 3D RAM
Abstract Redundancy repair is a commonly-used technique for memory yield improvement. In order to ensure high repair efficiency and final product yield, it is necessary to explore and develop the memory redundancy architecture carefully. However, due to the different failure distributions of memory arrays and various design constraints of memory architectures, it is difficult to explore the efficiency of the memory architecture thoroughly. In this paper, we propose a redundancy architecture exploration methodology to find the redundancy architecture with highest repair rate under redundancy constraints. Given a set of design constraints, failure distributions, and memory architectures, our methodology can explore at least $3(^{log}_{2}^{M*$ $log}_{2}^{N*$ $log}_{2}^{S})$ redundancy architectures systematically, where M, N, and S are the address sizes of memory row and column in a die, and the number of slices in the memory cube, respectively. In our experiments, the repair rates of 10 different 3D redundancy architectures with 3 different redundancy analysis algorithms in a given failure pattern distribution are simulated. The experimental result shows that the difference of the repair rates between the most efficient and least efficient memory redundancy architectures is up to 49.42%.
Description Author affiliation: Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan (Bing-Yang Lin; Mincent Lee; Cheng-Wen Wu)
ISBN 9780769550800
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2013-11-18
Publisher Place Taiwan
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 667.46 kB
Page Count 6
Starting Page 1
Ending Page 6

Source: IEEE Xplore Digital Library