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Author Wardle, C.L. ♦ Watson, C.R. ♦ Wilson, C.A. ♦ Mudge, J.C. ♦ Nelson, B.J.
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©1984
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations
Subject Keyword Macrocell networks ♦ Routing ♦ Very large scale integration ♦ Power generation ♦ Signal generators ♦ Wiring ♦ Binary trees ♦ Australia ♦ Signal design ♦ Chip scale packaging
Abstract This paper describes Sprint, an IC design system. Sprint is an integrated, hierarchical approach to VLSI design. All nodes (cells) in the hierarchy are abstracted in terms of their structural, electrical, and functional properties. Cells may be of arbitrary size and aspect ratio. The relative placement of cells is specified by the designer, and signal and power routing is automatically generated. Sprint has been successfully used by a six-person team to design a 100,000 transistor chip. The chip has been fabricated in a 2.5 micron, double layer metal, HMOS process.
Description Author affiliation: VLSI Program, CSIRO, Adelaide, South Australia (Wardle, C.L.)
ISBN 0818605421
ISSN 0738100X
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 1984-06-25
Publisher Place USA
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 1.19 MB
Page Count 8
Starting Page 594
Ending Page 601


Source: IEEE Xplore Digital Library