Access Restriction

Author Riahi, P.A. ♦ Navabi, Z. ♦ Lombardi, F.
Sponsorship IEEE Comput. Sci. Test Technol. Tech. Council
Source IEEE Xplore Digital Library
Content type Text
Publisher Institute of Electrical and Electronics Engineers, Inc. (IEEE)
File Format PDF
Copyright Year ©2003
Language English
Subject Domain (in DDC) Technology ♦ Engineering & allied operations ♦ Applied physics
Subject Keyword Hardware design languages ♦ Integrated circuit testing ♦ Logic circuit testing ♦ Combinational logic circuits
Abstract In this paper we are presenting a test methodology for performing module-bused mixed level fault simulation and test generation on System-on-Chip (SOC) combinational Intellectual Property (IP) cores for which both a pre-synthesis behavioral description and a post-synthesis netlist is available but in an analyzer output intermediate format not readable by core integraters. We use the Verilog Procedural Interface (VPI) to access and perform serial fault simulation on a pre-compiled core available as a mixed behavioral structural level design. We also use VPI to prepare a testbench environment for performing random pattern test generation. The simulation time results of applying this VPI-based test methodology on ISCAS85 Verilog benchmarks are also presented and compared to the flat (non-mixed level) version the proposed VPI-based environment.
Description Author affiliation: Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA (Riahi, P.A.; Navabi, Z.; Lombardi, F.)
ISBN 0769519512
ISSN 10817735
Educational Role Student ♦ Teacher
Age Range above 22 year
Educational Use Research ♦ Reading
Education Level UG and PG
Learning Resource Type Article
Publisher Date 2003-11-16
Publisher Place China
Rights Holder Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Size (in Bytes) 506.08 kB
Page Count 4
Starting Page 274
Ending Page 277

Source: IEEE Xplore Digital Library